1. Field
Exemplary embodiments of the present invention relate to an image sensor circuit, and more particularly, to a comparator capable of current compensation and noise reduction, and an analog-to-digital converter using the same.
2. Description of the Related Art
At the present time, with an increase in demands for a high frame rate of an image sensor, a read-out scheme of the image sensor has been changed from a serial analog-to-digital conversion (ADC) to a column parallel ADC in order to reflect the demands.
A single-slope ADC (SS-ADC) adapts the column parallel ADC scheme. In the column parallel ADC structure, since an ADC is arranged to each of columns, many more ADCs are necessary as an image size increases.
For this reason, the aforementioned conventional art has a concern that power noise such as current noise, which is generated in one column, is reflected in an image by an amount corresponding to the total number of columns (for example, about 2500 columns in a 5M CMOS image sensor). The power noise reflected in the image results in horizontal noise (HN). Furthermore, the conventional art has a concern that output noise is generated in every comparator of the ADC arranged at each of columns. The output noise is voltage noise kicked back from an output terminal of the comparator through a parasitic capacitor.